The present invention relates to methods and apparatus to ensure functionality and timing robustness in silicon-on-insulator (SOI) complementary metal oxide semiconductor (CMOS) circuits.
Silicon-on-insulator (SOI) technology is an enhanced silicon technology currently being utilized to increase the performance of digital logic circuits. By utilizing SOI technology, designers can increase the speed of digital logic integrated circuits or can reduce their overall power consumption. These advances in technology enable the development of more complex and faster integrated circuits that operate with less power.
An SOI transistor suffers from one inherent flaw. The floating body of the SOI transistor can develop a body charge over time. The amount of such floating body charge depends upon the potentials at the source, drain and gate of the SOI transistor. The maximum amount of charging occurs when the gate is completely turned off and both the source and drain electrodes are biased at the highest voltage supply Vdd. Given enough time, the body charge of the SOI transistor will eventually reach a saturation level. If a switching activity occurs for that device, a transient parasitic bipolar current can be induced in conjunction with the normal device drain current. The transient parasitic bipolar current causes the well known first cycle performance degradation. In multiplexer style SOI circuit topologies, such timing behavior variation is particularly troublesome.
A need exists for an improved and effective mechanism for to ensure functionality and timing robustness in silicon-on-insulator (SOI) complementary metal oxide semiconductor (CMOS) circuits.
Principal objects of the present invention are to provide methods and apparatus to ensure functionality and timing robustness in silicon-on-insulator (SOI) complementary metal oxide semiconductor (CMOS) circuits. Other important objects of the present invention are to provide such methods and apparatus to ensure functionality and timing robustness in silicon-on-insulator (SOI) complementary metal oxide semiconductor (CMOS) circuits substantially without negative effect and that overcome many of the disadvantages of prior art arrangements.
In brief, methods and apparatus are provided to ensure functionality and timing robustness in silicon-on-insulator (SOI) complementary metal oxide semiconductor (CMOS) circuits. A select signal for the SOI CMOS circuit is received. A floating body charge monitoring circuit is coupled to the SOI CMOS circuit for monitoring excess body charges in at least one predefined SOI device and providing an output control signal. A select signal adjusting circuit is coupled to the floating body charge monitoring circuit receiving the output control signal and the select signal and providing a conditionally adjusted select signal responsive to the output control signal of the floating body charge monitor circuit. The conditionally adjusted select signal is applied to the SOI CMOS circuit.
In accordance with features of the invention, the conditionally adjusted select signal provided by the select signal adjusting circuit responsive to the output control signal of the floating body charge monitor circuit includes a predefined delay at the trailing edge of the select signal extending the select signal pulse width. The conditionally adjusted select signal includes a shortened select signal pulse having a predefined delay at the rising edge of the select signal. The conditionally adjusted select signal includes a substantially unchanged select signal pulse width with a predefined delay of the rising edge of the select signal.